1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method thereof, for example, a Fin FBC (Floating Body Cell) memory device and a manufacturing method thereof.
2. Related Art
In recent years, an FBC memory device has been known as a semiconductor device expected to replace a 1T (Transistor)-1C (Capacitor) DRAM. The FBC memory device is configured so that FETs (Field Effect Transistors) each including a floating body (hereinafter, also “body”) are formed on an SOI (Silicon On Insulator) substrate. The FBC memory device stores data “1” or “0” in each FET according to the number of majority carriers accumulated in the body of the FET.
Recently, development of a fully depleted FBC (hereinafter, “FD-FBC”) is underway. If a memory device is made smaller in size, a gate length of the FD-FBC is smaller, accordingly. If the gate length is smaller, a threshold voltage difference between a memory cell storing therein data “0” (hereinafter, “0” cell) and a memory cell storing therein data “1” (hereinafter, “1” cell) is smaller. This causes a reduction in signal difference necessary for data discrimination.
To deal with the problem, an FBC memory device using FinFETs has been developed. However, a conventional Fin FBC needs a contact region for connecting each word line to a gate electrode. Due to this, a distance margin is required between each contact hole and an SOI layer to some extent. If FBCs configured as described above are arranged in a matrix, a size of a unit cell (cell size) is disadvantageously made large.
Moreover, in FIG. 12 of JP-A 2007-18588 (KOKAI), one plate electrode is formed integratedly with each plate line, so that no plate contacts are formed. However, if the plate lines are formed adjacent to the SOI layer (drain layer), a parasitic capacitance between each plate electrode and a drain increases. The increase in the parasitic capacitance between the plate electrode and the drain causes a reduction in an operation speed of the FBC and an increase in power consumption. Furthermore, if the plate lines are formed adjacent to the SOI layer (source layers or drain layers), a short circuit may possibly occurs between each plate electrode and either the source layer or the drain layer corresponding to the plate electrode. On the other hand, if the plate lines are formed to be separate from the SOI layer, the cell size of the FBC disadvantageously increases.